Late on the forum but here comes the answer. On PiStorm we use GPIO of Raspberry to communicate with FPGA. In turn the FPGA translates it to 680x0 alike bus protocol. The communication occurs only in short (few bytes) packets and is highly non-deterministic (depends on actual program flow in multitasking OS).People everywhere do have better CPU performance. Just not with PiStorm. Almost certainly a software issue, but difficult to tell from the PiStorm website. Cannot see why it would be because of the RP1.FYI, with the addition of the new rp1 or whatever it's called on the rpi5, you've made it unusable in a pistorm. Hope you know people were looking forward to even better performance.
The Pi5's GPIO is done by RP1 chip. The chip communicates with the BRCM through PCIe. While the PCIe itself is great for bulk transfers of larger amounts of data, it adds its own latency when the transmission is initiated. This is our performance killer. Due to the nature of transfers between Pi, FPGA and Amiga CPU bus, we cannot prepare larger communication packets in advance. In addition, the combination Pi+FPGA has only the time window of about 540ns mentioned before. Within this window we have to send data from Pi to FPGA, FPGA has to process it, perform communication through the CPU bus of the Amiga, and expose the result to the GPIO bus. Then, the software on Raspberry has to get this data back. Even if PCIe would add setup latency of 250ns for each initiated transfer, it would be too much for PiStorm needs. Two such transfers (one write, one read once FPGA is done) and almost whole time slot is wasted.
I do realize this is not something done by majority of raspberry users on daily basis, but for PiStorm very fast low-level GPIO bit-banging is absolutely mandatory. For that reason Pi5 (and probably CM5 in future if it uses RP1) is no-go for us.
Statistics: Posted by mee-how — Wed Jan 31, 2024 1:28 pm