Hi all,
I am experimenting with inter-core interrupts on the raspberry pi 4. I am using gic as the interrupt controller.
My understanding is that one has to enable those interrupts by writing to mailbox control registers, then write to mailbox set registers and the interrupt gets generated with a number between 32 and 47.
The problem I have is that those interrupts either don't get generated or don't reach any core. Is there any gotcha?
My code is roughly as follows:
where MAILBOX_CNTRL1 is 0xFF800054 and MBOX_SET04 is 0xFF800090. I am using low peri.
My interrupt handler does not get called for any interrupt being generated for mailbox on core 1, while it does get called for a system timer interrupt. The gic distributor and cpu interface are set up to route mailbox interrupts to the corresponding cores.
Am I doing something obviously wrong? Or am I missing something?
Thank you Image may be NSFW.
Clik here to view.
I am experimenting with inter-core interrupts on the raspberry pi 4. I am using gic as the interrupt controller.
My understanding is that one has to enable those interrupts by writing to mailbox control registers, then write to mailbox set registers and the interrupt gets generated with a number between 32 and 47.
The problem I have is that those interrupts either don't get generated or don't reach any core. Is there any gotcha?
My code is roughly as follows:
Code:
*MAILBOX_CNTRL1 = 1*MBOX_SET04 = 1My interrupt handler does not get called for any interrupt being generated for mailbox on core 1, while it does get called for a system timer interrupt. The gic distributor and cpu interface are set up to route mailbox interrupts to the corresponding cores.
Am I doing something obviously wrong? Or am I missing something?
Thank you Image may be NSFW.
Clik here to view.
Statistics: Posted by yaw moo — Thu Sep 05, 2024 3:49 am
