Have the CPU dump the FIFO. The packet standard and FIFO are the synchronization. Add an alignment marker to the packet if you want to. Reset the PIO state machine if misaligned.
Do not attempt a CPU read unless a full packet is there. Only dump a full frame. The state machine is blocking so it will create garbage if the CPU is the bottleneck. (DMA is capable of extending the FIFO depth.)
Warning you can go to SMT-4 on IO, which can cause a bottleneck. More than likely this will never matter for you.
Do not attempt a CPU read unless a full packet is there. Only dump a full frame. The state machine is blocking so it will create garbage if the CPU is the bottleneck. (DMA is capable of extending the FIFO depth.)
Warning you can go to SMT-4 on IO, which can cause a bottleneck. More than likely this will never matter for you.
Statistics: Posted by dthacher — Sat Nov 09, 2024 2:58 pm
