When reading PSRAM through QSPI interface, you have an overheard of at least16 QSPI clock cycles (24 bit address, suffix, wait/dummy, hold time) + 8 for transferring the data (32bit word) = 24 for each access.
In sequential mode (burst), you have only the initial overhead, then just 8 for each word.
If QSPI clock divider is 2, then double the figures to compare with single-cycle access of internal SRAM.
Once the QMI controller is configured, PSRAM is mapped transparently (similar to Flash) in the XIP memory window, by default in 3 locations:
• 0x11… : Cached XIP access
• 0x15… : Uncached XIP access
• 0x1d… : Uncached, untranslated XIP access — bypass QMI address translation
In sequential mode (burst), you have only the initial overhead, then just 8 for each word.
If QSPI clock divider is 2, then double the figures to compare with single-cycle access of internal SRAM.
Once the QMI controller is configured, PSRAM is mapped transparently (similar to Flash) in the XIP memory window, by default in 3 locations:
• 0x11… : Cached XIP access
• 0x15… : Uncached XIP access
• 0x1d… : Uncached, untranslated XIP access — bypass QMI address translation
Statistics: Posted by gmx — Mon Jan 06, 2025 12:21 am
