I checked the PLL setting in the 4 lane driver and the link frequency is set to 360MHz.
Sorry for my misunderstanding.
0x0301VTPXCK_DIV0x05
0x0303VTSYCK_DIV0x01
0x0304PREPLLCK_VT_DIV[3:0]0x03
0x0305PREPLLCK_OP_DIV[3:0]0x03
0x0306PLL_VT_MPY[10:8]0x00
0x0307PLL_VT_MPY[7:0]0x57
0x0309OPPXCK_DIV[4:0]0x0A
0x030BOPSYCK_DIV0x01
0x030CPLL_OP_MPY[10:8]0x00
0x030DPLL_OP_MPY[7:0]0x5A
INCK 24MHz / PLL_OP_DIV 3 * PLL_OP_MPY 90(0x5A) / 2 (DDR) = 360MHz
0x0301VTPXCK_DIV0x05
0x0303VTSYCK_DIV0x01
0x0304PREPLLCK_VT_DIV[3:0]0x03
0x0305PREPLLCK_OP_DIV[3:0]0x03
0x0306PLL_VT_MPY[10:8]0x00
0x0307PLL_VT_MPY[7:0]0x39
0x0309OPPXCK_DIV[4:0]0x0A
0x030BOPSYCK_DIV0x01
0x030CPLL_OP_MPY[10:8]0x00
0x030DPLL_OP_MPY[7:0]0x72
Need to switch the parameter accordingly.
Sorry for my misunderstanding.
0x0301VTPXCK_DIV0x05
0x0303VTSYCK_DIV0x01
0x0304PREPLLCK_VT_DIV[3:0]0x03
0x0305PREPLLCK_OP_DIV[3:0]0x03
0x0306PLL_VT_MPY[10:8]0x00
0x0307PLL_VT_MPY[7:0]0x57
0x0309OPPXCK_DIV[4:0]0x0A
0x030BOPSYCK_DIV0x01
0x030CPLL_OP_MPY[10:8]0x00
0x030DPLL_OP_MPY[7:0]0x5A
INCK 24MHz / PLL_OP_DIV 3 * PLL_OP_MPY 90(0x5A) / 2 (DDR) = 360MHz
For 2 lane mode, link frequency 456MHz, PLL should be as below.For mainline we really want to follow the manufacturer's datasheets as closely as possible, so that would mean matching the max data rate for 4 lane mode.
0x0301VTPXCK_DIV0x05
0x0303VTSYCK_DIV0x01
0x0304PREPLLCK_VT_DIV[3:0]0x03
0x0305PREPLLCK_OP_DIV[3:0]0x03
0x0306PLL_VT_MPY[10:8]0x00
0x0307PLL_VT_MPY[7:0]0x39
0x0309OPPXCK_DIV[4:0]0x0A
0x030BOPSYCK_DIV0x01
0x030CPLL_OP_MPY[10:8]0x00
0x030DPLL_OP_MPY[7:0]0x72
Need to switch the parameter accordingly.
Statistics: Posted by sohonomura2020 — Mon Jan 06, 2025 12:42 am